講座名稱：第二屆EDA國際研討會(huì)（ISEDA）

講座人：Jamal Deen 教授等

講座時(shí)間:5月10日9：00—5月13日18：00

講座地點(diǎn)：陜西賓館會(huì)議廳

講座內(nèi)容介紹：

報(bào)告題目：Compact Modeling of Organic/Polymeric Thin Film Transistors For Flexible Electronics

講座人：Jamal Deen，中科院外籍院士，麥克馬斯特大學(xué)杰出教授。于1985年獲得美國凱斯西儲(chǔ)大學(xué)博士學(xué)位。2007年當(dāng)選加拿大工程院士，2014年當(dāng)選歐洲科學(xué)與藝術(shù)院院士，同年當(dāng)選為加拿大皇家學(xué)會(huì)科學(xué)院院長。他在微納電子學(xué)、光電子學(xué)研究以及醫(yī)療電子學(xué)和環(huán)境科學(xué)中的應(yīng)用方面具有杰出貢獻(xiàn)，在重要國際學(xué)術(shù)刊物及會(huì)議發(fā)表論文580余篇。

報(bào)告摘要：In this presentation, we will discuss recent compact models and illustrate the merits and limitations of several of them as part of the electronic design automation platform. In this presentation, we will discuss our progress in developing industry-viable static and dynamic compact models for flexible transistors with predictable performance and the associated parameter extraction schemes including evolutionary computation for parameter extraction. Finally, we will present several on-going modeling challenges including illumination, hysteresis and contacts effects, as well as models that can predict stability, reliability, and lifetime.

報(bào)告題目：Dynamic Thermal Management and Adaptive Modeling for 3D AI Chips

講座人：David Atienza Alonso，瑞士洛桑聯(lián)邦理工學(xué)院電氣和計(jì)算機(jī)工程教授、嵌入式系統(tǒng)實(shí)驗(yàn)室（ESL）負(fù)責(zé)人和生態(tài)云可持續(xù)計(jì)算中心科學(xué)主任。他分別于2001年和2005年在西班牙UCM和比利時(shí)IMEC獲得計(jì)算機(jī)科學(xué)與工程碩士和博士學(xué)位。他的研究興趣包括高性能多處理器片上系統(tǒng)（MPSoC）和低功耗物聯(lián)網(wǎng)（IoT）系統(tǒng)的系統(tǒng)級(jí)設(shè)計(jì)方法，用于無線身體傳感器節(jié)點(diǎn)和智能嵌入式系統(tǒng)的超低功耗邊緣人工智能架構(gòu)、硬件/軟件可重構(gòu)系統(tǒng)、動(dòng)態(tài)內(nèi)存優(yōu)化和片上網(wǎng)絡(luò)設(shè)計(jì)。

報(bào)告摘要：In this talk, Prof. Atienza will review the basis of the recent innovative thermal modeling and prototyping approaches for non-uniform thermal characterization included in the open-source 3D Interlayer Cooling Emulator (3D-ICE). Then, in conjunction with a fast offline application profiling strategy utilizing gem5-X, the latest open-source architecture simulator for 2D/3D MPSoCs designs targeting AI chips, it will be shown how it is possible to develop a complete DTM evaluation framework that can be used to create Multi-Agent Reinforcement Learning (MARL) control schemes for different 3D MPSoCs and AI accelerators. Finally, it will be illustrated how this DTM framework based on MARL control can support advanced liquid cooling and electricity-generation technologies using microfluidic power cells for the next generation of energy-efficient 2D and 3D AI accelerators.

報(bào)告題目：Power-Aware LSI Testing: Present and Future

講座人：文曉青，日本九州理工學(xué)院教授。1986年獲中國清華大學(xué)文學(xué)學(xué)士學(xué)位，1990年獲日本廣島大學(xué)文學(xué)碩士學(xué)位，1993年獲日本大阪大學(xué)博士學(xué)位。他是IEEE計(jì)算機(jī)學(xué)會(huì)測試技術(shù)委員會(huì)（TTTC）功率感知測試技術(shù)活動(dòng)委員會(huì)的聯(lián)合創(chuàng)始人和聯(lián)合主席。他是IEEE院士，是《IEEE超大規(guī)模集成系統(tǒng)匯刊》（TVLSI）和《電子測試雜志：理論與應(yīng)用》（JETTA）的副主編。發(fā)表了300多篇論文，擁有43項(xiàng)美國專利和14項(xiàng)日本專利，他的研究方向包括LSI電路的設(shè)計(jì)、測試和診斷。

報(bào)告摘要：With low power consumption becoming a key requirement for advanced LSI designs, the gap between functional power and test power has kept growing to such an extent that power-aware testing has now become a must. The foundation of power-aware testing is a complete understanding of the global impact of switching activity on peak and average power as well as the local impact of switching activity on IR-drop-induced delay increase along data and clock paths. This talk presents a holistic view on various aspects of power-aware testing, aimed at helping researchers and engineers to develop more sophisticated and complete solutions for controlling LSI test power.

報(bào)告題目：The Hidden Interconnect (or Communication) Challenges

講座人：John Kim，韓國大田KAIST（韓國高等科學(xué)與技術(shù)研究所）電氣工程學(xué)院教授。他獲得了斯坦福大學(xué)的博士學(xué)位和康奈爾大學(xué)的理學(xué)學(xué)士學(xué)位。他曾獲得谷歌教師研究獎(jiǎng)、微軟亞洲新教師獎(jiǎng)學(xué)金，并被列入ISCA、MICRO和HPCA名人堂；曾參與英特爾和摩托羅拉的微處理器的設(shè)計(jì)。他的研究方向包括計(jì)算機(jī)體系結(jié)構(gòu)、互聯(lián)網(wǎng)絡(luò)、安全和移動(dòng)系統(tǒng)。

報(bào)告摘要：As compute and memory continue to scale, the interconnect or the communication is becoming a critical bottleneck in determining overall system performance and scalability. In this talk, I will present the challenges of the "hidden" interconnect that exists in modern systems in terms of its impact on the design, performance, reliability/security, and cost of the system. In particular, I will present case studies from recent interconnect architectures.

報(bào)告題目：Printed Computing: Design Automation and Computing based on Additive Printed Electronics

講座人：Mehdi B.Tahori,德國卡爾斯魯厄理工學(xué)院計(jì)算機(jī)科學(xué)系計(jì)算機(jī)科學(xué)與工程研究所（ITEC）教授，可靠納米計(jì)算（CDNC）主席。他分別于2003年和2002年獲得斯坦福大學(xué)電氣工程博士和碩士學(xué)位。曾擔(dān)任日本東京大學(xué)超大規(guī)模集成電路設(shè)計(jì)與教育中心（VDEC）客座教授、美國富士通實(shí)驗(yàn)室的高級(jí)計(jì)算機(jī)輔助研究科學(xué)家，從事深亞微米混合信號(hào)超大規(guī)模集成（VLSI）設(shè)計(jì)的可靠性問題。

報(bào)告摘要：Printed electronics offer certain technological advantages over their silicon-based counterparts, such as mechanical flexibility, low process temperatures, maskless and additive manufacturing possibilities. Neverteless, due to low device count, large feature sizes and high variabilities, originated in low-cost additive manufacturing, existing design automation and computing paradigms of digital VLSI are not applicable to printed electronics. This talk covers the technology, process, modeling, fabrication, design automation, and computing paradigms for circuits and systems based on additive printed technologies.

主辦單位：集成電路學(xué)部